Prototypes

1. NoC prototypes: full design data available
Here is a list of past and current NoC prototyping efforts either on FPGAs or as VLSI circuits. If you know of others and wanted them listed here please let me know. These are efforts where design data are publicly available:

CONfigurable NEtwork Creation Tool (CONNECT), CMU – Online BlueSpec SystemVerilog generator for NoCs that are “FPGA-friendly”, 2012
NetMaker (University of Cambridge) – FPGA, 2009
Open Noc (Linköpings Universitet) – FPGA, 2007
Mini NoC (Technische Universiteit Eindhoven) – FPGA, 2006

2. NoC prototypes: partial/no/promised design data available
Here is a list of people, publications, or pointers to reported NoC prototypes; however, no complete design data are publicly available:

Atlas (GAPH, PUCRS, Brazil. One can simulate different NoC topologies and generate VHDL files, which then could be synthesized. The authors reported FPGA implementation.) – 2011
NoCGen: an environment for the Hermes NoC emulation (Grenoble Institute of Technology). NoCGen uses the Hermes NoC developed by the PUCRS of Porte Allegre, Brazil. – FPGA, 2011
NoCBench, Tampere University of Technology. Only limited design data are available. That includes some libs too.) – 2009.

3. Router prototypes
Here is a list of efforts that focused on the router architecture. VHDL/Verilog implementations available.
Open source NoC router (Stanford. A parameterized RTL implementation of a state-of-the-art VC router.) – 2013

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7 Responses to Prototypes

  1. Erkka says:

    We at Tampere University of Technology (www.tut.fi/dcs) have built several MPSOC prototypes on FPGA, utilizing both hierarhical bus and 2D mesh.
    For example, my colleague’s PhD thesis presents many measurement results from FPGA
    [Ari Kulmala, “Scalable Multiprocessor System-on-chip Architecture
    Design on FPGA”, PhD Thesis, Tampere University of Technology, Publication 793, 2009. Available: http://www.tkt.cs.tut.fi/research/daci/pub_open/Kulmala-Ari_PhD_Scalable_Multiprocessor_System-on-chip_Architecture.pdf%5D. See especially Publication 3, pages 142-163.
    It is true that all design data is not available yet. However, some parts are, see for example http://www.tkt.cs.tut.fi/research/nocbench/ and http://opencores.org/project,funbase_ip_library

  2. Korotkyi Ievgen says:

    Hello. I created synthesizable verilog design of network on chip with link aggregation: http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6141403
    There is also exists fast SystemC model of this NoC.
    If my scientific advisor will not mind I plan to make this project open source to the end of the year.
    Every person who interested in collaboration is invited to contact with me: korotkiy.eugene@ieee.org

  3. Ramesh says:

    I had written vhdl code of mesh and torus topologies now i want to calculate the parameters like power,delay,throughput and test with one real life application how can I proceed cany one guide me in this respect. please reply soon.

  4. rohit says:

    pls anybody provide me mesh and torus topology verilog code…….@…….gitecrohit@gmail.com

  5. adnan ahmad says:

    I am working on virtual channel router in order to improve the performance of noc router but i need VHDL code for virtual channel router so can any one send me the code i will appreciate that .thanks

  6. Nizam Alias says:

    pls anybody provide me mesh 3×3 topology vhdl code…….@…….nizam9312@gmail.com

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