What is the most popular full-system simulator?

All right, it’s time for a new post on this blog!

So, I teach a course on Computer Architecture and as part of the course activities we do paper reviews on topics like caches, memory designs, processor architecture, etc. Each year I try to refresh some of the papers that are reviewed. I usually check first conferences such as ISCA, HPCA, MICRO, and HIPEAC. I also try to identify papers that present results using GEM5 full system simulator because that is what we use in some hw assignments and projects; this way students see some connections between what people publish and the hw assignments… 🙂

If anyways I browsed the papers, I thought it’d be a good idea to collect stats about what simulators and other related tools people in the computer architecture community use. Here is an approximate breakdown (for now just ISCA). It seems that GEM5 is still one of the favorites for many researchers. I would love to know how many companies (such as AMD, Intel, etc.) are actually using these tools.


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What is the most cited reference in the NoC community?

Would you say that if some work is the most cited reference regarding a specific concept, it would represent the reference that introduced that concept? Who is considered/credited for introducing the network-on-chip concept? Based on the number of citations, it seems that reference [4] below might be the one, even though some older references had already discussed the concept. While [4] used the term “on chip network”, today, arguably, “network on chip” discussed in [3] is the term that is more popular :-). Do you know of any other candidate reference or do you know some insight story regarding the emergence of the NoC concept? If so, please let me know and I’ll include it here.
(Updated on 2015.April.10; thanks Joel for the updated numbers)

[1] C. Seitz, Let’s route packets instead of wires, Advanced Research in VLSI: Proceedings of the Sixth MIT Conference, 1990. CITED BY 46; NOTE: AT SYSTEM LEVEL, INTER-CHIP
[2] P. Guerrier and A. Greiner, A generic architecture for on-chip packet-switched interconnections, DATE, March 2000. CITED BY 1009
[3] A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg, and D. Lindqvist, Network on Chip: an architecture for billion transistor era, IEEE NorChip Conference, Nov. 2000. CITED BY 426
[4] W.J. Dally and B. Towles, Route packets, not wires: on-chip interconnection networks, ACM/IEEE Design Automation Conference (DAC), June 2001. CITED BY 3153
[5] L. Benini and G. De Micheli, Networks on chips: a new SoC paradigm, Computer, vol. 35, no. 1, pp. 70-78, 2002. CITED BY 3365

Posted in Network-on-Chip, Online articles, Opinions | 5 Comments

Where does the money go?

Now, I have not written a new post for a while… I was thinking about it and I realized that while we have been looking at tools, teaching materials, calls for papers, etc., we have not looked at funding. How much money is placed on NoC research? And where does the money go? So, I did a quick search on NSF award advanced-search. I used the following Keyword: “NoC” “on-chip” “network-on-chip” “networks-on-chip” “interconnection network”. The search returned 264 awards. More than half of the results are not really related to NoCs, but other than that the rough distribution is:

Less than or equal $50,000 (5)
Between $50,001 – $100,000 (11)
Between $100,001 – $500,000 (211)
Between $500,001 – $1,000,000 (22)
More than $1,000,000 (7)

If we click on Refine Search by state, we can see the number of awards by state. Here are the top 5 “lion share”s 🙂 :
California (27)
Pennsylvania (24)
Texas (21)
Massachusetts (20)
Michigan (14)

If you want to browse individual awards description, here is the link.

Posted in Network-on-Chip | 2 Comments

Top 5 most popular NoC simulators

It turns out that this NoC Blog is visited a lot because people search for “NoC simulator”. So, I decided to try to find out what simulators are the most popular. Please participate. If you used or are using an NoC simulator vote for it here.

Posted in Simulators, tools | 3 Comments

Wanted: collaboration

This post is an experiment; it is kind of a craigslist for NoCs. Its purpose is to foster networking and collaboration (in addition to the traditional “methods” of: networking done via conference participation, or friends of friends, or friends of advisor :-), or sending email with question about published paper). If it will work out, then I will make it more formal. For the time being we will use the method of leaving comments to this post. The idea of this post came to me from a recent comment on a different post, Prototypes, of this blog. If you are a (NoC) researcher and are looking for collaborators in the area of NoC please leave a comment here with the specific NoC topic on which you work or plan to work and look for collaborators. Potential collaborators then could contact you directly.
For example, if you developed a say adaptive routing algorithm, which you already verified with an NoC simulator, but also wanted to validate it on a say “some system like a video decoder” FPGA prototype, you may want to look for someone with prior experience to collaborate with on this aspect and in this way get it done faster.

Posted in NoC Classifieds | 11 Comments


1. NoC prototypes: full design data available
Here is a list of past and current NoC prototyping efforts either on FPGAs or as VLSI circuits. If you know of others and wanted them listed here please let me know. These are efforts where design data are publicly available:

CONfigurable NEtwork Creation Tool (CONNECT), CMU – Online BlueSpec SystemVerilog generator for NoCs that are “FPGA-friendly”, 2012
NetMaker (University of Cambridge) – FPGA, 2009
Open Noc (Linköpings Universitet) – FPGA, 2007
Mini NoC (Technische Universiteit Eindhoven) – FPGA, 2006

2. NoC prototypes: partial/no/promised design data available
Here is a list of people, publications, or pointers to reported NoC prototypes; however, no complete design data are publicly available:

Atlas (GAPH, PUCRS, Brazil. One can simulate different NoC topologies and generate VHDL files, which then could be synthesized. The authors reported FPGA implementation.) – 2011
NoCGen: an environment for the Hermes NoC emulation (Grenoble Institute of Technology). NoCGen uses the Hermes NoC developed by the PUCRS of Porte Allegre, Brazil. – FPGA, 2011
NoCBench, Tampere University of Technology. Only limited design data are available. That includes some libs too.) – 2009.

3. Router prototypes
Here is a list of efforts that focused on the router architecture. VHDL/Verilog implementations available.
Open source NoC router (Stanford. A parameterized RTL implementation of a state-of-the-art VC router.) – 2013

Posted in Prototypes | 8 Comments

Fish fight

Recently Synopsys acquired Magma. This made me think of the recent lawsuit from the world of on-chip networks of Sonics against Arteris. What I mean is this possible scenario: A big fish sues a smaller fish. The lawsuit battle will drain a lot of financial resources from both fish. However, the smaller fish will likely suffer more from this and its price will decrease significantly (I know this because for example Magma’s stock price plummeted after being sued by Synopsys back in 2004; at the time I had just joined Magma and the value of my hiring stocks options vanished over night :-)). Once the smaller fish is cheap and possibly recovering: buy it. At the end of the day, lawyers prosper and have nice exotic “sea-food dinners” all around the Bay Area :-). Writing this reminded me of a recent video I watched: Debate on the Proposition that Software Patents Encourage Innovation. I could not agree more with Prof. Edward A. Lee.

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