This post is an experiment; it is kind of a craigslist for NoCs. Its purpose is to foster networking and collaboration (in addition to the traditional “methods” of: networking done via conference participation, or friends of friends, or friends of advisor 
, or sending email with question about published paper). If it will work out, then I will make it more formal. For the time being we will use the method of leaving comments to this post. The idea of this post came to me from a recent comment on a different post, Prototypes, of this blog. If you are a (NoC) researcher and are looking for collaborators in the area of NoC please leave a comment here with the specific NoC topic on which you work or plan to work and look for collaborators. Potential collaborators then could contact you directly.
For example, if you developed a say adaptive routing algorithm, which you already verified with an NoC simulator, but also wanted to validate it on a say “some system like a video decoder” FPGA prototype, you may want to look for someone with prior experience to collaborate with on this aspect and in this way get it done faster.
Wanted: collaboration
Prototypes
1. Prototypes: full design data available
Here is a list of past and current NoC prototyping efforts either on FPGAs or as VLSI circuits. If you know of others and wanted them listed here please let me know. These are efforts where design data are publicly available:
– Mini NoC (Technische Universiteit Eindhoven) – FPGA, 2006
– Open Noc (Linköpings Universitet) – FPGA, 2007
– NetMaker (University of Cambridge) – FPGA, 2009
2. Prototypes: partial/no/promised design data available
Here is a list of people, publications, or pointers to reported NoC prototypes; however, no complete design data are publicly available:
– Atlas (GAPH, PUCRS, Brazil. One can simulate different NoC topologies and generate VHDL files, which then could be synthesized. The authors reported FPGA implementation.) – 2011
– NoCGen: an environment for the Hermes NoC emulation (Grenoble Institute of Technology). NoCGen uses the Hermes NoC developed by the PUCRS of Porte Allegre, Brazil. – FPGA, 2011
– NoCBench, Tampere University of Technology. Only limited design data are available. That includes some libs too.) – 2009.
Fish fight
Recently Synopsys acquired Magma. This made me think of the recent lawsuit from the world of on-chip networks of Sonics against Arteris. What I mean is this possible scenario: A big fish sues a smaller fish. The lawsuit battle will drain a lot of financial resources from both fish. However, the smaller fish will likely suffer more from this and its price will decrease significantly (I know this because for example Magma’s stock price plummeted after being sued by Synopsys back in 2004; at the time I had just joined Magma and the value of my hiring stocks options vanished over night ). Once the smaller fish is cheap and possibly recovering: buy it. At the end of the day, lawyers prosper and have nice exotic “sea-food dinners” all around the Bay Area . Writing this reminded me of a recent video I watched: Debate on the Proposition that Software Patents Encourage Innovation. I could not agree more with Prof. Edward A. Lee.
In the news
This entry will be continuously edited: it is meant to function as a news feed with links to online articles.
Epiphany, multicore programming online articles
William Wong recently wrote two online articles. The first article is on Adapteva’s Epiphany 32-bit, single precision floating-point multicore architecture (its eMesh consists of 13 networks: this reminds me of a point that professor Anant Agarwal made in his NOCS’11 keynote speech: NoCs are cheap, so just throw them on to the chip), which targets low-power embedded applications. The second article is on multicore programming.
Multicore Array Targets Embedded Applications
Get Ready For Some Hard Work With Multicore Programming
To publish or to patent?
I wonder how many of the people from the NoC community are aware of patents
in this area. I recently run into some and was not too surprised.
I guess that when one does not see too many papers published by researchers
from given institutions/corporations, one should expect some activity on the
patents front instead.
Here are some examples; I’ll leave it to you to figure out what’s new:
http://www.freepatentsonline.com/result.html?query_txt=network+on+chip&sort=relevance&srch=top&search=
http://www.faqs.org/patents/inventor/eric-o-mejdrich-rochester-us-1/
(note that one is even called simply “network on chip” )
Research groups
Here is a list (alphabetical order) of groups involved in NoC research. This is a list of groups not of people. This list is far from being complete! New entries are added all the time. If you want/think your group to be listed here, please let me know.
BONE NoC Research Group, KAIST, Korea
Carbon Research Group, MIT
Comcas
EOLAB at University of Cagliari
Hardware Design Support Group (GAPH), Brazil
Integrated systems lab at EPFL
Integrated CMOS Photonics at MIT
Intel
Lightwave Research Laboratory at Columbia
Li-Shiuan Peh (LSP) group at MIT
Mobile Computing System Lab, Hong Kong
NaNoC design platform
NoCBench at Tampere University of Technology, Finland
Nostrum at KTH
NOC Research Group, Institute MD, University of Rostock
Parallel architectures group (GAP) at Universidad Politécnica de Valencia
Stanford interconnection network research
System level design (SLD) group at CMU
System level design group at Columbia
Technion
